module t_segled #(
    parameter CNT_MAX = 25'd25_000_000
)  (
    input sys_clk,
    input sys_rst_n,
    input [3:0] num_list [5:0], // 数码管显示的值
    output reg[5:0] seg_sel,
    output reg [7:0] seg_led
);
    reg [24:0] cnt_500us;
    reg [3:0] count;
    reg [7:0] temp;

    // 分频500us，用于刷新位选信号
    always@(posedge sys_clk or negedge sys_rst_n)begin
        if(!sys_rst_n)
            cnt_500us <= 25'b0;
        else if(cnt_500us < CNT_MAX/1000)
            cnt_500us = cnt_500us + 25'b1;
        else
            cnt_500us <= 25'b0;
    end

    // 计数
    always @(posedge sys_clk or negedge sys_rst_n) begin
        if(!sys_rst_n)
            count <= 4'b0;
        else if(cnt_500us == CNT_MAX/1000 - 1'b1)begin
            if(count < 3'd5)
                count <= count + 4'b1;
            else
                count <= 4'b0;
        end
    end

    // 位选
    always @(posedge sys_clk or negedge sys_rst_n) begin
        if(!sys_rst_n)
            seg_sel <= 6'b111110;
        else
            case(count)
                3'd0: seg_sel <= 6'b111110;
                3'd1: seg_sel <= 6'b111101;
                3'd2: seg_sel <= 6'b111011;
                3'd3: seg_sel <= 6'b110111;
                3'd4: seg_sel <= 6'b101111;
                3'd5: seg_sel <= 6'b011111;
                default: seg_sel <= 6'b111110;
            endcase
    end

    // 段选
    always @(posedge sys_clk or negedge sys_rst_n) begin
        if(!sys_rst_n)
            seg_led <= 8'b0;
        else begin
            temp <= num_list[count];
            case(num_list[count])
                4'h0: seg_led <= 8'b1100_0000; // 0
                4'h1: seg_led <= 8'b1111_1001; // 1
                4'h2: seg_led <= 8'b1010_0100; // 2
                4'h3: seg_led <= 8'b1011_0000; // 3
                4'h4: seg_led <= 8'b1001_1001; // 4
                4'h5: seg_led <= 8'b1001_0010; // 5
                4'h6: seg_led <= 8'b1000_0010; // 6
                4'h7: seg_led <= 8'b1111_1000; // 7
                4'h8: seg_led <= 8'b1000_0000; // 8
                4'h9: seg_led <= 8'b1001_0000; // 9
                4'hA: seg_led <= 8'b1000_1000; // A
                4'hB: seg_led <= 8'b1000_0011; // B
                4'hC: seg_led <= 8'b1100_0110; // C
                4'hD: seg_led <= 8'b1010_0001; // D
                4'hE: seg_led <= 8'b1000_0110; // E
                4'hF: seg_led <= 8'b1000_1110; // F
                default: seg_led <= 8'b1100_0000; // 默认显示0
            endcase
            
        end
    end

endmodule